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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adsp-21mod980 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 multiport internet gateway processor features performance complete single-chip multiport internet gateway processor (no external memory required) implements sixteen modem channels or forty voice channels in one package each processor can implement one v.34/v.90 data/ fax modem (includes datapump and controller) standard power version: 600 mips sustained perfor- mance, 13.3 ns instruction time @ 2.75 v (internal) low power version: 600 mips sustained performance, 13.3 ns instruction time @ 1.80 v (internal) open architecture extensible to voice-over-network (von) and other applications low power dissipation, 45 mw (typical) per channel power-down mode featuring low cmos standby power dissipation integration adsp-2100 family code-compatible, with instruction set extensions 2.00m bytes of on-chip sram, configured as 1.125m bytes of program memory and 0.875m bytes of data memory dual-purpose program memory, for both instruction and data storage 352-ball pbga with a 1.9 square inch (1225 square mm) footprint system configuration 16-bit internal dma port for high-speed access to on-chip memory (mode-selectable) programmable multichannel serial port supports 24/32 channels two double-buffered serial ports with companding hardware and automatic data buffering separate reset pins for each internal processor functional block diagram iad<15:0>, idma cntl pf<0:2> /mode a:c 20 3 17 4 4 8 4 20 sport1 sport0a clkin emulator data<23:8>, a<0> sport0b iad<15:0>, idma cntl 218x 1 218x 2 218x 3 218x 4 218x 5 218x 6 218x 7 218x 8
rev. 0 adsp-21mod980 C2C general description the adsp-21mod980 is a multiport internet gateway processor optimized for implementation of a complete v.34/56k modem. all data pump and controller functions can be implemented on a single device, offering the lowest power consumption and high- est possible modem port density. the adsp-21mod980 combines the adsp-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the adsp-21mod980 integrates 2.0m bytes of on-chip memory, configured as 384k words (24-bit) of program ram, and 448k words (16-bit) of data ram. power-down circuitry is also pro- vided to reduce the average and standby power consumption of equipment which, in turn, reduces equipment cooling require- ments. the adsp-21mod980 is available in a 35 sq-mm., 352-lead pbga package. fabricated in a high-speed, low-power, cmos process, the adsp-21mod980 operates with a 13.3 ns instruction cycle time. every instruction can execute in a single processor cycle. the adsp-21mod980? flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. in one processor cycle, the adsp-21mod980 can: generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation this takes place while the processor continues to: receive and transmit data through the two serial ports receive and/or transmit data through the internal dma port receive and/or transmit data through the byte dma port decrement timer modem software the modem software executes general modem control, command sets, error correction and data compression, data modulations (for example, v.90 and v.34), and host interface functions. the host interface allows system access to modem statistics, such as call progress, connect speed, retrain count, symbol rate, and other modulation parameters. the modem data pump and controller software resides in on- chip sram and does not require additional memory. the adsp-21mod980 can be dynamically configured by download- ing software from the host through the 16-bit dma interface. this sram-based architecture provides a software upgrade path to other applications, such as voice-over-ip (voip), and to future standards. the modem software is available as object code. development system the adsp-2100 family development software, a complete set of tools for software and hardware system development, sup- ports the adsp-21mod980. the system builder provides a high-level method for defining the architecture of systems under development. the assembler has an algebraic syntax that is easy to program and debug. the linker combines object files into an executable file. the simulator provides an interactive instruction- level simulation with a reconfigurable user interface to display different portions of the hardware environment. a prom splitter generates prom programmer-compatible files. the c compiler, based on the free software foundation? gnu c compiler, generates adsp-21mod980 assembly source code. the source code debugger allows programs to be corrected in the c environment. the runtime library includes over 100 ansi-standard mathematical and dsp-specific functions. the adsp-218x ez-ice emulator aids in the hardware debugging of an ad sp-21mod980 system. the ez-ice, in conjunction with the required processor selection hardware, allows the user to independently debug code on individual modem processors. the emulator consists of hardware, host computer resident software, and target board connector. the adsp- 21mod980 i ntegrates on-chip emulation support with a 14-pin ice-port interface. the adsp-21mod980 device need not be removed from the target system when using the ez-ice, nor are any adapters needed. due to the small footprint of the ez-ice connector, emulation can be supported in final board designs. the ez-ice performs a full range of functions, including: in-target operation up to 20 breakpoints single-step or full-speed operation registers and memory values can be examined and altered pc upload and download functions instruction-level emulation of program booting and execution complete assembly and disassembly of instructions c source-level debugging see ?esigning an ez-ice-compatible target system?in the adsp-2100 family ez-tools manual (adsp-2181 sections), as well as the designing an ez-ice compatible system section of this data sheet, for the exact specifications of the ez-ice target board connector. additional information this data sheet provides a general overview of adsp-21mod980 functionality. for specific information about the modem processors, refer to the adsp-2188m preliminary data sheet. for additional information on the architecture and instruction set of the modem processors, refer to the adsp-2100 family user? manual, third edition. for more information about the development tools, refer to the adsp-2100 family development tools data sheet. ez-ice is a registered trademark of analog devices, inc.
rev. 0 C3C adsp-21mod980 architecture overview figure 1 is an overall block diagram of the adsp-21mod980 multiport internet gateway processor. it contains eight inde- pendent digital signal processors. every modem processor has: a dsp core 256k bytes of ram two serial ports a dma port the signals of each modem processor are accessed through the external pins of the adsp-21mod980. some signals are bused with the signals of the other processors and are accessed through a single ext ernal pin. other signals remain separate and are accessed through separate external pins for each processor. the arrangement of the eight modem processors in the adsp-21m od980 makes one basic configuration possible: a slave configuration. in this configuration, the data pins of all eight processors connect to a single bus structure. all eight modem processors have identical functions and equal status. each of the four modem processors are connected to a common dma bus and each modem processor is configured to operate in the same mode (see the slave mode and the memory mode descriptions in the memory architecture section. the slave mode is considered to be the only mode of operation in the adsp-21mod980 modem pool. serial ports the adsp-21mod980 has a multichannel serial port (sport) connected to each internal digital modem processor for serial communications. the following is a brief list of adsp-21mod980 sport fea- tures. for additional information on the internal serial ports, refer to the adsp-2100 family user? manual . each sport: is bidirectional and has a separate, double-buffered transmit and receive section. can use an external serial clock or generate its own serial clock internally. has independent framing for the receive and transmit sections. sections run in a frameless mode, or with frame synchroniza- tion signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulse- widths and timings. supports serial data word lengths from 3 to 16 bits and pro- vides optional a-law and -law companding according to ccitt recommendation g.711. receive and transmit sections can generate unique interrupts on completing a data word transfer. can receive and transmit an entire circular buffer of data with one overhead cycle per data word. an interrupt is generated after a data buffer transfer. a multichannel interface selectively receives and transmits a 24- or 32-word, time-division multiplexed, serial bitstream. idma cntl = ial, ird, iwr, iack interrupts= irqe (pf4), irql0 (pf5), irql1 (pf6), irq2 (pf7) emulator = ems , eint , elin, ebr , ebg , eclk, elout, ereset sport 0a, sport 0b = rfs0, dr0, dt0. sclk0 sport 1 = rfs1, tfs1, dr1, sclk1 8 8 8 8 8 8 8 8 32 br<8:1> bg<8:1> reset <8:1> clkout<8:1> ee<8:1> is <8:1> tfs0<8:1> dt1<8:1> interrupts <8:1> gnd v ddint v ddext 109 44 22 subtotal = 175 power balls total = 352 balls subtotal = 177 signal balls signals routed to each respective die note: 1) pwd and pf3/mode d are tied high iad<15:0>, idma cntl pf<0:2> /mode a:c 20 3 17 4 4 8 4 20 sport1 sport0a clkin emulator data<23:8>, a<0> sport0b iad<15:0>, idma cntl 218x 1 218x 2 218x 3 218x 4 218x 5 218x 6 218x 7 218x 8 figure 1. adsp-21mod980 processor pool
rev. 0 adsp-21mod980 C4C pin descriptions the adsp-21mod980 is available in a 352-lead pbga package. in order to maintain maximum functionality and reduce pack- age size and pin count, some serial port, programmable flag, interrupt, and external bus pins have dual, multiplexed func- tionality. the external bus pins are configured during reset only, while serial port pins are software configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. in cases where pin functional- ity is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. common-mode pins # input/ pin of out- name(s) pins put function reset 8 i processor reset input br 8 i bus request input bg 8 o bus grant output irq2/ 8 i edge- or level-sensitive in terrupt request 1 pf7 i/o programmable i/o pin irql0/ 8 i level-sensitive interrupt request 1 pf5 i/o programmable i/o pin irql1/ 8 i level-sensitive interrupt requests 1 pf6 i/o programmable i/o pin irqe/ 8 i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin mode c/ 1 i mode select input?hecked only pf2 during reset i/o programmable i/o pin during normal operation mode b/ 1 i mode select input?hecked only pf1 during reset i/o programmable i/o pin during normal operation mode a/ 1 i mode select input?hecked only pf0 during reset i/o programmable i/o pin during normal operation clkin 1 i clock input clkout 8 o processor clock output sport 28 i/o serial port i/o pins 2 v dd and gnd 175 i power and ground ez-port 16 i/o for emulation use notes 1 inte rrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, the modem pool will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 sport configuration determined by the modem pool? system control regis- ter. software configurable. memory interface pins the adsp-21mod980 modem pool is used in slave mode. in slave mode, the modem processors operate in host configura- tion. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the modem pool is running. see the memory architecture section for more information. host pins (mode c = 1) modem processors 1? # input/ pin of out- name(s) pins put function iad15:0 32 i/o idma port address/data bus a0 1 o address pin for external i/o, program, data, or byte access d23:8 16 i/o data i/o pins for program, data byte and i/o spaces iwr 2 i idma write enable ird 2 i idma read enable ial 2 i idma address latch pin is 8 i idma select iack 2 o idma port acknowledge configurable in mode d; open drain interrupts the interrupt controller allows each modem proces sor in the modem pool to respond individually to 11 possible interrupts and reset with minimum overhead. the adsp-21mod980 pro- vides four dedicated external interrupt input pins, irq2 , irql1 , irql0 , and irqe (shared with the pf7:4 pins) for each modem processor. the adsp-21mod980 also supports internal inter- rupts from the timer, the byte dma port, the serial port, software, and the power-down control circuit. the interrupt levels are internally prioritized and individually maskable ( except power- down and reset). the irq2 , irq1 , and irq0 input p ins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level-sensitive and irqe is edge-sensitive. the pri- orities and vector addresses of all interrupts are shown in table i. table i. interrupt priority and interrupt vector addresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 (highest priority) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 (lowest priority) when the modem pool is reset, interrupt servicing is disabled. low power operation the adsp-21mod980 has three low-power modes that signifi- cantly reduce the power dissipation when the device operates under standby conditions. these modes are: power-down idle slow idle the clkout pin may also be disabled to reduce external power dissipation.
rev. 0 adsp-21mod980 C5C power-down the adsp-21mod980 modem pool has a low-power feature that lets the modem pool enter a very low-power dormant state through software control. here is a brief list of power-down fea- tures. refer to the adsp-2100 family user? manual , ?ystem interface?chapter, for detailed information about the power- down feature. quick recovery from power-down. the modem pool begins executing instructions in as few as 200 clkin cycles. support for an externally generated ttl or cmos processor clock. the external clock can continue running during power- down without affecting the lowest power rating and 200 clkin cycle recovery. power-down is initiated by the software power-down force bit. interrupt support allows an unlimited number of instructions to be executed before optionally powering down. context clear/save control allows the modem pool to continue where it left off or start with a clean context when leaving the power-down state. the reset pin also can be used to terminate power-down. idle when the ads p-21mod980 is in the idle mode, the modem pool waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruc- tion. in idle mode idma, bdma, and autobuffer cycle steals still occur. slow idle the idle instruction is enhanced on the adsp-21mod980 to let the modem pool? internal clock signal be slowed, further reducing power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is: idle ( n ); where n = 16, 32, 64, or 128. this instruction keeps the modem pool fully functional, but operating at the slower clock rate. while it is in this state, the modem pool? other internal clock signals, such as sclk, clkout, and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle ( n ) instruction is used, it effectively slows down the modem pool? internal clock and thus its response time to incoming interrupts. the one-cycle response time of the stan- dard idle state is increased by n, the clock divisor. w hen an enabled interrupt is received, the adsp-21mod980 will remain in the idle state for up to a maximum of n modem pool cycles ( n = 16, 32, 64, or 128) before resuming normal operation. when the idle ( n ) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the modem pool? reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the modem pool takes to come out of the idle state (a maximum of n cycles). system configuration figure 2 shows the hardware interfaces for a typical multichan- nel modem configuration with the adsp-21mod980. other system design considerations, such as host processing require- ments, electrical loading, and overall bus timing, must all be met. a line interface can be used to connect the multichannel subscriber or client data stream to the multichannel serial port of the adsp-21mod980. the idma port of the adsp- 21mod980 is used to give a host processor full access to the internal memory of the adsp-21mod980. this lets the host dynamically configure the adsp-21mod980 by loading code and data into its internal memory. this configuration also lets the host access server data directly from the adsp-21mod980? internal memory. in this configuration, the modem processors should be put into host memory mode where mode c = 1, mode b = 0, and mode a = 1. adsp-21 mod 980 sport idma st/cntl adsp-21 mod 980 sport idma st/cntl t1/e1 line interface host micro host control host address host data status and control pal idma pal idma control idma address status and control figure 2. multichannel modem configuration
rev. 0 adsp-21mod980 C6C clock signals the adsp-21mod980 is clocked by a ttl-compatible clock signal that runs at half the instruction rate; a 37.5 mhz input clock yields a 13.3 ns processor cycle, which is equiv alent to 75 mhz. normally, instructions are executed in a single proces- sor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. the clock input signal is connected to the processor? clkin input. the clkin input cannot be halted, changed during operation, or operated below the specified frequency during normal operation. the only exception is while the processor is in the power-down state. for additional information, refer to chapter 9, adsp- 2100 family user? manual for a detailed explanation of this power-down feature. a clock output (clkout) signal is generated by the processor at the processor? cycle rate. reset the reset signals initiate a reset of each modem processor in the adsp-21mod980. the reset signals must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to let the internal clocks stabilize. if reset s are activated any time after power up, the clocks continue to run and do not require stabilization time. the power-up sequence is defined as the total time required for the oscillator circuits to stabilize after a valid v dd is applied to the processors, and for the internal phase-locked loops (pll) to lock onto the specific frequency. a minimum of 2000 clkin cycles ensures that the plls have locked, but this does not include the oscillators?start-up time. during this power-up sequence, the reset signals should be held low. on any subsequent resets, the reset signals must meet the minimum pulsewidth specification, t rsp . the reset inputs contains some hysteresis; however, if an rc circuit is used to generate the reset signals, the use of exter- nal schmitt triggers is recommended. the reset for each individual modem processor sets the internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat register. when a reset is released, if there is no pending bus request and the modem processor is configured for booting, the boot-loading sequence is performed. the first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. memory architecture the adsp-21mod980 provides a variety of memory and peripheral interface options for modem processor 1. the key functional groups are program memory, data memory, byte memory, and i/o. refer to the following figures and tables for pm and dm memory allocations in the adsp-21mod980. the adsp-21mod980 modem pool operates in one memory mode: slave mode. the following figures and tables describe the memory of the adsp-21mod980: figure 3 shows program memory. figure 4 shows data memory. table ii explains the generation of address bits based on the pmovlay values. table iii explains the generation of address bits based on the dmovlay values. access to external memory is not available.
rev. 0 adsp-21mod980 C7C accessible when pmovlay = 7 0x2000 ?0x3fff accessible when pmovlay = 6 8k internal mode b = 0 addr 8k internal pmovlay = 0, 4, 5, 6, 7 0x3fff 0x1fff 0x0000 program memory 0x2000 accessible when pmovlay = 5 accessible when pmovlay = 4 0x2000 ?0x3fff accessible when pmovlay = 0 0x2000 ?0x3fff 0x2000 ?0x3fff pm mode b = 0 always accessible at address 0x0000 ?0x1fff internal memory 0x2000 ?0x3fff program memory figure 3. program memory table ii. pmovlay bits pmovlay memory a13 a12:0 0, 4, 5, 6, 7 internal not applicable not applicable accessible when dmovlay = 8 0x0000 0x1fff accessible when dmovlay = 7 0x0000 0x1fff accessible when dmovlay = 6 32 memory mapped registers 0x3fff internal 8160 words data memory addr 0x3fe0 8k internal dmovlay = 0, 4, 5, 6, 7, 8 0x1fff 0x3fdf 0x2000 accessible when dmovlay = 5 accessible when dmovlay = 4 0x0000 0x1fff accessible when dmovlay = 0 0x0000 0x1fff 0x0000 0x1fff data memory always accessible at address 0x2000 0x3fff internal memory 0x0000 0x1fff figure 4. data memory map table iii. dmovlay bits dmovlay memory a13 a12:0 0, 4, 5, 6, 7, 8 internal not applicable not applicable
rev. 0 adsp-21mod980 C8C 1 dwait 111101100000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iowait3 iowait2 iowait1 iowait0 wait state mode select 0 = normal mode (pwait, dwait, iowait0 3 = n wait states, ranging from 0 to 7) 1 = 2n + 1 mode (pwait, dwait, iowait0 3 = 2n + 1 wait states, ranging from 0 to 15) dm(0x3ffe) figure 5. wait state control register 1 dm(0x3fe6) pftype 0 = input 1 = output cmssel 0 = disable cms 1 = enable cms (where bit: 11-iom, 10-bm, 9-dm, 8-pm) bmwait 111101100000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 figure 6. programmable flag and composite select control register note: since they are multiplexed within the adsp-21mod980, pf[2:0] should be configured as an output for only one processor at a time. bit [3] of dm (0x3f36) must also be 0. 0 dm(0x3fff) reserved set to 0 000010000000111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sport0 enable 0 = disable 1 = enable sport1 enable 0 = disable 1 = enable sport1 configure 0 = fi, fo, irq0, irq1, sclk 1 = sport1 reserved always set to 0 pwait program memory wait states disable bms 0 = enable bms 1 = disable bms, except when memory strobes are three-stated figure 7. system control register table iv. adsp-21mod980 mode of operation mode c mode b mode a booting method 1 0 1 idma feature is used to load internal memory as desired. program execution is held off until internal program memory location 0x0000 is written to. chip is configured in slave mode. 1 iack requires external pull-down. 1 1 considered standard operating settings. these configurations simplify your design and improve memory management. idma timing de tails and the correct usage of iack are described in the a dsp-2100 family user? manual; refer to pages 11-18 thru 11-19. memory-mapped registers (new to the adsp-21mod980) the adsp-21mod980 has three memory-mapped registers that differ from other adsp-21xx family dsps. the slight modifi- cations to these registers (wait state control, programmable flag and composite select control, and system control) provide the adsp-21mod980? wait state and bms control features. slave mode this section describes the slave mode memory configuration of the modem processors. internal memory dma port (idma port) the idma port provides an efficient way for a host system and the adsp-21mod980 to communicate. the port is used to access the on-chip program memory and data memory of each modem processor with only one processor cycle per word over- head. the idma port cannot be used, however, to write to the processor? memory-mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer. 2. host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selection into the processor? idma control registers. if iad [15] = 1, the value of iad [7:07] represents the idma overlay: iad[14:8] must be set to 0. if iad [15] = 0, the value of iad [13:0] represents the starting address of internal memory to be accessed and iad [14] reflects pm or dm for access. 3. host uses is and ird (or iwr ) to read (or write) processor internal memory (pm or dm). 4 . host ends idma transfer.
rev. 0 C9C adsp-21mod980 the idma port has a 16-bit multiplexed add ress and data bus and supports 24-bit program memory. the idma port is completely asynchronous and can be written to, while the adsp-21mod980 is operating at full speed. the processor memory address is latched and then automati- cally incremented after each idma transaction. an external device can, therefore, access a block of sequentially addressed memory by specifying only the starting address of the block. this increases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle . when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location, the destination type specifies whether it is a dm or pm access. the falling edge of the address latch signal latches this value into the idmaa register. once the address is stored, data can then be either read from, or written to, the adsp-21mod980? on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the adsp-21mod980 that a par- ticular transaction is required. in either case, there is a one- processor-cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is automati- cally incremented, and another access can occur. through the idmaa register, the processor can also specify the starting address and data format for dma operation. asserting the idma port select ( is ) and address latch enable (ial) directs the adsp-21mod980 to write the address onto the iad [14:0] bus into the idma control register. if iad [15] is set to 0, idma latches the address. if iad [15] is set to 1, idma latches ovlay memory. the idmaa register is memory mapped at address dm (0x3fe0). note that the latched address (idmaa) or overlay register cannot be read back by the host. the idma overlay register is memory mapped at address dm(0x3fe7). see figure 8 for more in formation on idma memory map- ping. when bit 14 in 0x3fe7 is set to 1, timing in figure 25 applies for short reads. when bit 14 in 0x3fe7 is set to zero short reads, use the timing shown in figure 26. 0 dm(0x3fe7) reserved set to 0 000010000000111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 short read only enable 0 = disable 1 = enable id dmovlay id pmovlay reserved set to 0 a. idma overlay dm(0x3fe0) idmaa address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 idmad destination memory type: 0 = pm 1 = dm uuuuuuuuuuuuuuu b. idma control (u = undefined at reset) figure 8. idma control/ovlay registers
rev. 0 adsp-21mod980 C10C accessible when dmovlay = 8 accessible when dmovlay = 7 0x0000 0x1fff 0x0000 0x1fff accessible when pmovlay = 7 0x2000 0x3fff accessible when pmovlay = 6 accessible when pmovlay = 5 accessible when pmovlay = 4 0x2000 0x3fff accessible when pmovlay = 0 0x2000 0x3fff 0x2000 0x3fff always accessible at address 0x0000 0x1fff 0x2000 0x3fff dma program memory ovlay dma data memory ovlay accessible when dmovlay = 6 accessible when dmovlay = 5 accessible when dmovlay = 4 0x0000 0x1fff accessible when dmovlay = 0 0x0000 0x1fff 0x0000 0x1fff always accessible at address 0x2000 0x3fff 0x0000 0x1fff figure 9. direct memory accesspm and dm memory maps idma port booting the adsp-21 mod980 boots programs through its internal dma port. when mode c = 1, mode b = 0, and mode a = 1, the adsp-21mod980 boots from the idma port. idma feature can load as much on-chip memory as desired. program execu- tion is held off until on-chip program memory location 0 is written to. flag i/o pins each modem processor has eight general-purpose program- mable in put/output flag pins. they are controlled by two memory-m apped registers. the pftype register determines the direction, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the adsp- 21mod980? c lock. bits that are programmed as outputs will read the value being output. the pf pins default to input dur- ing reset. note: pins pf0, pf1, and pf2 are also used for device con- figu ration during reset. since they are multiplexed within the adsp-21mod980, pf[0:2] should be configured as an output for only one processor at a time. designing an ez-ice-compatible system the adsp-21mod980 has on-chip emulation support and an ice-port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation, without replacing the target system processor, by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ice? in-circuit pro be, a 14-pin plug. the ez-ice can emulate only one modem processor at a time. you must include hardware to select which processor in the adsp-21mod980 you want to emulate. figure 10 is a functional representation of the modem processor selection hardware. one ice-port connector can be used with two adsp-21mod980 processors without using additional buffers. issuing the ?hip reset?command during emulation causes the modem processor to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. as the mode pins share functionality with pf0:2 on the adsp-21mod980, it may be necessary to reset the target hardware separately to ensure the proper mode selection state on emulator chip reset. see the adsp-2100 fam- ily ez-tools data sheet for complete information on ice products.
rev. 0 adsp-21mod980 C11C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bg br eint elin eclk ems ereset gnd ebg ebr key elout ee reset bg6 br6 reset6 ee6 bg7 br7 reset7 ee7 bg5 br5 reset5 ee5 bg4 br4 reset4 ee4 bg3 br3 reset3 ee3 bg2 br2 reset2 ee2 bg1 br1 reset1 ee1 bg0 br0 reset0 ee0 elout ebr ebg eint elin eclk ems ereset adsp-21 mod980 %
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'()#& *+ the ice-port interface consists of the following adsp-21mod980 pins: ebr ems elin ebg eint elout ereset eclk ee these adsp-21mod980 pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull-down resistors. the traces for these signals between the adsp-21mod980 and the connector must be kept as short as possible, no longer that 3 inches. the following pins are also used by the ez-ice: br reset bg gnd the ez-ice uses the ee (emulator enable) signal to take con- trol of the adsp-21mod980 in the target system. this causes the processor to use its ereset , ebr , and ebg pins instead of the reset , br , and bg pins. the bg output is three-stated. these signals do not need to be jumper-isolated in a system. the ez-ice connects to the target system via a ribbon cable and a 14-pin female plug. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.
rev. 0 adsp-21mod980 C12C target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 10. this connector must be added to the target board design in order to use the ez-ice. be sure to allow enough room in the system to fit the ez-ice probe onto the 14-pin connector. 12 34 56 78 910 11 12 13 14 top view gnd ebg ebr key (no pin) elout ee reset bg br eint elin eclk ems ereset figure 11. target board connector for ez-ice the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tion?in 7 must be removed from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spac- ing should be 0.1 0.1 inches. the pin strip header must have at least 0.15 inch clearance on all sides to accept the ez-ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie, and samtec. target memory interfac e for a target system to be compatible with the ez-ice emul ator, it must comply with the memory interface guidelines listed below. target system interface signals when the ez-ice board is installed, the performance on some system signals change. design your system to be compatible with the following system interface signal changes introduced by the ez-ice board: ez-ice emulation introduces an 8 ns propagation delay between target circuitry and the processor on the reset signal. ez-ice emulation introduces an 8 ns propagation delay between target circuitry and the processor on the br signal. ez-ice emulation ignores reset and br when si ngle- stepping. ez-ice emulation ignores reset and br when in emulator space (processor halted). ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the processor? external memory bus only if bus grant ( bg ) is asserted by the ez-ice board? processor.
rev. 0 adsp-21mod980 C13C specifications recommended operating conditions parameter min max unit v ddext 2.97 3.63 v v ddint 2.61 2.89 v t amb 070 c electrical characteristics parameter test conditions min typ max unit v ih , hi-level input voltage 1, 2 @ v ddint = max 1.5 v v ih , hi-level clkin voltage @ v ddint = max 2.0 v v il , lo-level input voltage 1, 3 @ v ddint = min 0.7 v v oh , hi-level output voltage 1, 4 , 5 @ v ddext = min, 2.0 v i oh = ?.5 ma @ v ddext = 3.0 v, 2.4 v i oh = ?.5 ma @ v ddext = min, v ddext 0.3 v v ddext 0.3 i oh = ?00 a 6 v ol , lo-level output voltage 1, 4, 5 @ v ddext = min, 0.4 v i ol = 2 ma i ih , hi-level input current 3 @ v ddint = max, 10 a v in = 3.6 v i il , lo-level input current 3 @ v ddint = max, 10 a v in = 0 v i ozh , three-state leakage current 7 @ v ddext = max, 10 a v in = 3.6 v 8 i ozl , three-state leakage current 7 @ v ddext = max, 10 a v in = 0 v 8 i dd , supply current (idle) 9 @ v ddint = 2.75, 80 ma t ck = 13.3 ns i dd , supply current (dynamic) 10 @ v ddint = 2.75, 373 ma t ck = 13.3 ns 11 , t amb = 25 c i dd , supply current (power-down) 12 lowest power mode 200 ma c i , input pin capacitance 1, 3, 6, 9 @ v in = 2.5 v, 64 pf f in = 1.0 mhz, t amb = 25 c c o , output pin capacitance 1, 6, 7, 12, 10 @ v in = 2.5 v, 64 pf f in = 1.0 mhz, t amb = 25 c notes 1 bidirectional pins: rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, iad [15:0], pf[2:0], pf[7:4]. 2 input only pins: reset , br , dr0, dr1, is , ial, ird , iwr . 3 input only pins: clkin, reset , br , dr0, dr1. 4 output pins: bg , a0, dt0, dt1, clkout, iack . 5 although specified for ttl outputs, all adsp-21mod980 outputs are cmos-compatible and will drive to v ddext and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, iad[15:0], rfs1. 8 0 v son br . 9 applies to pbga package type. 10 output pin capacitance is the capacitive load for any three-stated output pin. 11 v in = 0 v and 3 v. for typical supply current figures refer to power dissipation section. 12 see the adsp-2100 family user? manual for details. specifications subject to change without notice.
rev. 0 adsp-21mod980 C14C absolute maximum ratings parameter min max internal supply voltage (v ddint ) ?.3 v +3.0 v external supply voltage (v ddext ) ?.3 v +4.6 v input voltage 1 ?.5 v +4.6 v output voltage swing 2 ?.5 v v ddext + 0.5 v storage temperature range ?5 c +150 c notes 1 applies to bidirectional pins (d0?23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1?13, pf0?f7) and input only pins (clkin, reset , br , dr0, dr1). 2 applies to output pins ( bg , pwdack, a0, dt0, dt1, clkout). timing parameters general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, the user cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. the user has no control over this timing?ircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell what the processor will do in a given circumstance. switching characteristics can also be used to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the proces- sor operates correctly with other devices. memory timing specifications the table below shows common memory device specifications and the corresponding adsp-21mod980 timing parameter. frequency dependency for timing specifications t ck is defined as 0.5 t cki . the adsp-21mod980 uses an input clock with a frequency equal to half the instruction rate: a 37.5 mhz input clock (which is equivalent to 26.6 ns) yields a 13.3 ns processor cycle (equivalent to 75 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing param eters to obtain the specification value. example: t ckh = 0.5 t ck ?5 ns = 0.5 (13.3 ns) ?5 ns = 1.67 ns environmental conditions ambient temperature rating: t amb =t case ?(pd ja ) t j = junction temperature in c pd = power dissipation in w ja = thermal resistance (junction-to-ambient) package ja airflow pbga 28.2 c/w 0 lfm caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21mod980 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 adsp-21mod980 C15C power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: data memory is accessed every fourth cycle with 50% of the address pins switching. data memory writes occur every fourth cycle with 50% of the data pins switching. each address and data pin has a 64 pf total load at the pin. the application operates at v dd = 3.3 v and t ck = 13.3 ns. total power dissipation = p int + ( c v dd 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 12). ( c v dd 2 f ) is calculated for each output: table v. example of calculating power dissipation # of pins c v dd 2 f address, dms 8 64 pf 3.3 2 v 18.8 mhz = 104.9 mw data output, wr 9 64 pf 3.3 2 v 18.8 mhz = 117.9 mw 222.8 m w total power dissipation for this example is p int + 222.8 mw. 1/t ck mhz power (p int ) mw 75 45 50 55 60 65 70 230 250 270 290 310 330 350 370 390 410 80 400mw 373mw 340mw 278mw 256mw 240mw v dd = 2.9v v d d = 2.6v v d d = 2.75v valid for all temperature grades 1. power reflects device operating with no output loads. 2. typical power dissipation at 25 c 3. i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1,4,5,12,13,14), 30% are type 2 and type 6, and 20% are idle instructions. figure 12. power vs. frequency capacitive loading figures 13 and 14 show the capacitive loading characteristics of the adsp-21mod980. c l pf rise time (0.4v 2.4v) ns 30 300 0 50 100 150 200 250 25 15 10 5 0 20 t a = 85 c v dd = 0v to 2.0v figure 13. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) c l pf 14 0 valid output delay or hold ns 50 100 150 250 200 12 4 2 2 10 8 nominal 16 18 6 4 6 figure 14. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature)
rev. 0 adsp-21mod980 C16C test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high-impedance state. the out- put disable time (t dis ) is the difference of t measured and t decay , as shown in figure 16. the time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approximated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured t decay is calculated. if multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. 1.5v output, input 1.5v figure 15. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, see figure 16. if multiple pins (such as the data bus) are enabled, the mea- surement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 16. output enable/disable to output pin 50pf 1.5v i oh i ol figure 17. equivalent device loading for ac measure- ments (including all fixtures)
rev. 0 adsp-21mod980 C17C timing parameters 75 mhz parameter m i n max unit clock signals and reset timing requirements : t cki clkin period 26.6 80 ns t ckil clkin width low 8 ns t ckih clkin width high 8 ns switching characteristics: t ckl clkout width low 0.5 t ck 2ns t ckh clkout width high 0.5 t ck 2ns t ckoh clkin high to clkout high 0 13 ns control signals timing requirements : t rsp reset width low 5 t ck 1 ns t ms mode setup before reset high 2 ns t mh mode setup after reset high 5 ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles, assuming stable clkin (not including crystal oscillator start-up time). t ms t ckil t ckoh t ckh t ckl t cki t ckih t mh clkin clkout pf (2:0)* reset *pf2 is mode c, pf1 is mode b, pf0 is mode a figure 18. clock signals
rev. 0 adsp-21mod980 C18C parameter min max unit interrupts and flags timing requirements : t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25 t ck + 10 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25 t ck ns switching characteristics : t foh flag output hold after clkout low 5 0.25 t ck 5ns t fod flag output delay from clkout low 5 0.5 t ck + 4 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on t he following cycle. (refer to interrupt controller operation in the program control chapter of the adsp-2100 family user s manual , third edition, for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , irql0 , irql1 , irqe . 4 pfx = pf0, pf1, pf2, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, flag_out 4 . t ifh t ifs clkout irqx fi pfx figure 19. interrupts and flags
rev. 0 adsp-21mod980 C19C timing parameters parameter min max unit serial ports timing requirements : t sck sclk period 26.67 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclkin width 12 ns switching characteristics : t cc clkout high to sclkout 0.25 t ck 0.25 t ck + 6 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 12 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 12 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 12 ns t scdd sclk high to dt disable 12 ns t rdv rfs (multichannel, frame delay zero) to dt valid 12 ns t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv t tdv t scdv t rd t scp t sck t scp t rdv t tde t tdv clkout sclk dr tfs in rfs in rfs out tfs out dt tfs out alternate frame mode rfs out multichannel mode, frame delay 0 (mfd = 0) tfs in alternate frame mode rfs in multichannel mode, frame delay 0 (mfd = 0) figure 20. serial ports
rev. 0 adsp-21mod980 C20C parameter min max unit idma address latch timing requirements : t ialp duration of address latch 1, 2 10 ns t iasu iad15 0 address setup before address latch end 2 5ns t iah iad15 0 address hold after address latch end 2 2ns t ika iack low before start of address latch 2, 3 0ns t ials start of write or read after address latch end 1, 2 3ns t iald address latch start after address latch end 1, 2 2ns notes 1 start of address latch = is low and ial high. 2 end of address latch = is high or ial low. 3 start of write or read = is low and iwr low or ird low. t ika t ialp t iald t ials t iasu t iasu t iah t iah t ialp iack ial is iad15 0 ird or iwd figure 21. idma address latch
rev. 0 adsp-21mod980 C21C timing parameters parameter min max unit idma write, short write cycle timing requirements : t ikw iack low before start of write 1 0ns t iwp duration of write 1, 2 10 ns t idsu iad15 0 data setup before end of write 2, 3, 4 3ns t idh iad15 0 data hold after end of write 2, 3, 4 2ns switching characteristic : t ikhw start of write to iack high 10 ns notes 1 start of write = is low and iwr low. 2 end of write = is high or iwr high. 3 if write pulse ends before iack low, use specifications t idsu , t idh . 4 if write pulse ends after iack low, use specifications t iksu , t ikh . iad15 0 iack is iwr data t ikhw t ikw t idsu t iwp t idh figure 22. idma write, short write cycle
rev. 0 adsp-21mod980 C22C parameter min max unit idma write, long write cycle timing requirements : t ikw iack low before start of write 1 0ns t iksu iad15 0 data setup before end of write 2, 3, 4 0.5 t ck + 5 ns t ikh iad15 0 data hold after end of write 2, 3, 4 0ns switching characteristics : t iklw start of write to iack low 4 1.5 t ck ns t ikhw start of write to iack high 10 ns notes 1 start of write = is low and iwr low. 2 if write pulse ends before iack low, use specifications t idsu , t idh . 3 if write pulse ends after iack low, use specifications t iksu , t ikh . 4 this is the earliest time for iack low from start of write. for idma write cycle relationships, please refer to the adsp-2100 family user s manual, third edition. iad15 0 iack is iwr data t ikhw t ikw t iksu t iklw t ikh figure 23. idma write, long write cycle
rev. 0 adsp-21mod980 C23C timing parameters parameter min max unit idma read, long read cycle timing requirements : t ikr iack low before start of read 1 0ns t irk end of read after iack low 2 2ns switching characteristics : t ikhr iack high after start of read 1 10 ns t ikds iad15 0 data setup before iack low 0.5 t ck 2ns t ikdh iad15 0 data hold after end of read 2 0ns t ikdd iad15 0 data disabled after end of read 2 10 ns t irde iad15 0 previous data enabled after start of read 0 ns t irdv iad15 0 previous data valid after start of read 10 ns t irdh1 iad15 0 previous data hold after start of read (dm/pm1) 3 2 t ck 5ns t irdh2 iad15 0 previous data hold after start of read (pm2) 4 t ck 5ns notes 1 start of read = is low and ird low. 2 end of read = is high or ird high. 3 dm read or first half of pm read. 4 second half of pm read. t irk t ikr previous data read data t ikhr t ikds t irdv t irdh t ikdd t irde t ikdh iack is ird iad15 0 figure 24. idma read, long read cycle
rev. 0 adsp-21mod980 C24C parameter min max unit idma read, short read cycle 1 timing requirements : t ikr iack low before start of read 2 0ns t irp duration of read 10 ns switching characteristics : t ikhr iack high after start of read 2 10 ns t ikdh iad15 0 data hold after end of read 3 0ns t ikdd iad15 0 data disabled after end of read 3 10 ns t irde iad15 0 previous data enabled after start of read 0 ns t irdv iad15 0 previous data valid after start of read 10 ns t irdh1 iad15 0 previous data hold after start of read (dm/pm1) 4 2t ck 5ns t irdh1 iad15 0 previous data hold after start of read (pm2) 5 t ck 5ns notes 1 timing applies to adsp-21mod980 when short read only is disabled. see next page. 2 start of read = is low and ird low. 3 end of read = is high or ird high. 4 dm read or first half of pm read. 5 second half of pm read. t ikr previous data t ikhr t irdv t irdh t ikdd t irde t ikdh iack is ird iad15 0 new read data figure 25. idma read, short read cycle
rev. 0 adsp-21mod980 C25C timing parameters parameter min max unit idma read, short read cycle in short read only mode 1 timing requirements : t ikr iack low before start of read 2 0ns t irp duration of read 1 10 ns switching characteristics : t ikhr iack high after start of read 2 10 ns t ikdh iad15 0 data hold after end of read 3 0ns t ikdd iad15 0 data disabled after end of read 3 10 ns t irde iad15 0 previous data enabled after start of read 0 ns t irdv iad15 0 previous data valid after start of read 10 ns notes 1 short read only is enabled by setting bit 14 of the idma overlay register to 1 (0x3fe7). short read only can be enabled by the processor core writing to the register or by an external host writing to the register. disabled by default. 2 start of read = is low and ird low. previous data remains until end of read. 3 end of read = is high or ird high. t irp t ikr previous data t ikhr t irdv t ikdd t irde t ikdh iack is ird iad15 0 figure 26. idma read, short read cycle
rev. 0 adsp-21mod980 C26C pinout?op view left 1 2 3 4 5 6 7 8 9 10 11 12 13 a gnd a0 v ddint v ddint gnd pf0 v ddext v ddext v ddext clkout_2 gnd dt1_2 v ddext b iad1_a gnd v ddint iad0_a gnd pf1 v ddext v ddext v ddext pf6_2 gnd gnd br_2 c iad4_a iad2_a gnd ird_a gnd pf2 v ddext ial_a v ddext pf4_2 gnd tfs0_2 ee_2 d iad14_a iad5_a iad3_a gnd gnd is_1 v ddext iwr_a v ddext pf5_2 gnd pf7_2 reset_2 e dr0a iad13_a clkin iad15_a f gnd gnd bg_1 gnd g clkout_1 gnd gnd br_1 h gnd gnd gnd gnd j reset_1 tfs0_1 rfs0a pf7_1 k v ddext v ddext v ddext v ddext l v ddext v ddext v ddext v ddext m pf4_1 pf5_1 pf6_1 ee_1 n gnd gnd gnd gnd p sclk0a dt0a dt1_1 clkout_6 r v ddint v ddint v ddint bg_6 t pf4_6 pf6_6 gnd iack_a u gnd gnd dt1_6 br_6 v pf5_6 pf7_6 iad11_a iad6_a w gnd gnd gnd gnd y tfs0_6 ee_6 iad9_a iad7_a aa reset_6 iad10_a is_4 iad12_a ab v ddint v ddint v ddint v ddint ac clkout_4 pf4_4 pf5_4 gnd bg_4 gnd is_6 gnd br_4 gnd reset_7 gnd ee_7 ad pf6_4 gnd gnd gnd gnd iad8_a gnd gnd pf6_7 clkout_7 gnd gnd dt1_7 ae gnd gnd pf7_4 gnd tfs0_4 rfs1 dr1 gnd ee_4 gnd pf5_7 gnd v ddint af gnd dt1_4 tfs1 gnd sclk1 reset_4 pf4_7 gnd pf7_7 gnd tfs0_7 gnd v ddint 1 2 3 4 5 6 7 8 9 10 11 12 13
rev. 0 adsp-21mod980 C27C pinout?op view right 14 15 16 17 18 19 20 21 22 23 24 25 26 is_2 v ddext gnd v ddext pf7_3 gnd gnd gnd d23 d22 d21 d18 gnd a v ddext v ddext gnd v ddext pf6_3 gnd tfs0_3 gnd v ddext d19 d17 gnd d16 b v ddext v ddext gnd v ddext pf5_3 gnd clkout_3 gnd reset_3 d20 gnd d15 d14 c bg_2 v ddext gnd v ddext pf4_3 gnd gnd dt1_3 v ddext gnd d13 d12 d11 d ems d10 d09 ereset e d08 is_3 bg_3 ebg f ee_3 pf5_5 br_3 ebr g gnd gnd gnd gnd h eclk elout elin eint j v ddext v ddext v ddext v ddext k iad11_b clkout_5 pf4_5 iad10_b l iad8_b iad9_b iad12_b iad6_b m tfs0_5 br_5 pf7_5 iad7_b n v ddint v ddint v ddint v ddint p gnd gnd bg_5 pf6_5 r reset_5 gnd dt1_5 ee_5 t gnd gnd gnd gnd u iad1_b iad2_b is_5 iad0_b v gnd iad3_b iad4_b iad5_b w iwr_b ird_b ial_b is_8 y gnd gnd gnd gnd aa v ddint v ddint v ddint v ddint ab v ddext v ddext is-7 gnd pf6_8 v ddext tfs0_8 gnd reset_8 gnd iad14_b iad15_b iack_b ac v ddext bg_7 gnd gnd pf4_8 v ddext rfs0b gnd gnd gnd gnd bg_8 iad13_b ad v ddext br_7 gnd gnd pf5_8 v ddext dt1_8 gnd ee_8 gnd sclk0b gnd br_8 ae v ddext clkout_8 gnd gnd pf7_8 v ddext dt0b gnd dr0b gnd v ddint v ddint gnd af 14 15 16 17 18 19 20 21 22 23 24 25 26
rev. 0 adsp-21mod980 C28C the adsp-21mod980 package pinout is shown in the table below. 352-ball pbga package pinout signal ball signal ball signal ball signal ball signal ball name number name number name number name number name number a0 a2 d11 d26 ee_1 m4 gnd ac12 gnd af1 bg_1 f3 d12 d25 ee_2 c13 gnd ac17 gnd af4 bg_2 d14 d13 d24 ee_3 g23 gnd ac21 gnd af8 bg_3 f25 d14 c26 ee_4 ae9 gnd ac23 gnd af10 bg_4 ac5 d15 c25 ee_5 t26 gnd ad2 gnd af12 bg_5 r25 d16 b26 ee_6 y2 gnd ad3 gnd af16 bg_6 r4 d17 b24 ee_7 ac13 gnd ad4 gnd af17 bg_7 ad15 d18 a25 ee_8 ae22 gnd ad5 gnd af21 bg_8 ad25 d19 b23 eint j26 gnd ad7 gnd af23 br_1 g4 d20 c23 elin j25 gnd ad8 gnd af26 br_2 b13 d21 a24 elout j24 gnd ad11 gnd b2 br_3 g25 d22 a23 ems e23 gnd ad12 gnd b5 br_4 ac9 d23 a22 ereset e26 gnd ad16 gnd b11 br_5 n24 dr0a e1 gnd a1 gnd ad17 gnd b12 br_6 u4 dr0b af22 gnd a5 gnd ad21 gnd b16 br_7 ae15 dr1 ae7 gnd a11 gnd ad22 gnd b19 br_8 ae26 dt0a p2 gnd a16 gnd ad23 gnd b21 clkin e3 dt0b af20 gnd a19 gnd ad24 gnd b25 clkout1 g1 dt1_1 p3 gnd a20 gnd ae1 gnd c3 clkout_2 a10 dt1_2 a12 gnd a21 gnd ae2 gnd c5 clkout_3 c20 dt1_3 d21 gnd a26 gnd ae4 gnd c11 clkout_4 ac1 dt1_4 af2 gnd aa23 gnd ae8 gnd c16 clkout_5 l24 dt1_5 t25 gnd aa24 gnd ae10 gnd c19 clkout_6 p4 dt1_6 u3 gnd aa25 gnd ae12 gnd c21 clkout_7 ad10 dt1_7 ad13 gnd aa26 gnd ae16 gnd c24 clkout_8 af15 dt1_8 ae20 gnd ac4 gnd ae17 gnd d4 d08 f23 ebg f26 gnd ac6 gnd ae21 gnd d5 d09 e25 ebr g26 gnd ac8 gnd ae23 gnd d11 d10 e24 eclk j23 gnd ac10 gnd ae25 gnd d16
rev. 0 adsp-21mod980 C29C signal ball signal ball signal ball signal ball signal ball name number name number name number name number name number gnd d19 gnd w23 iad8_b m23 pf5_5 g24 sclk0b ae24 gnd d20 iack_a t4 iad9_a y3 pf5_6 v1 sclk1 af5 gnd d23 iack_b ac26 iad9_b m24 pf5_7 ae11 tfs0_1 j2 gnd f1 iad0_a b4 ial_a c8 pf5-8 ae18 tfs0_2 c12 gnd f2 iad0_b v26 ial_b y25 pf6_1 m3 tfs0_3 b20 gnd f4 iad1_a b1 ird_a c4 pf6_2 b10 tfs0_4 ae5 gnd g2 iad1_b v23 ird_b y24 pf6_3 b18 tfs0_5 n23 gnd g3 iad10_a aa2 is_1 d6 pf6_4 ad1 tfs0_6 y1 gnd h1 iad10_b l26 is_2 a14 pf6_5 r26 tfs0_7 af11 gnd h2 iad11_a v3 is_3 f24 pf6_6 t2 tfs0_8 ac20 gnd h3 iad11_b l23 is_4 aa3 pf6_7 ad9 tfs1 af3 gnd h4 iad12_a aa4 is_5 v25 pf6_8 ac18 v ddext a7 gnd h23 iad12_b m25 is_6 ac7 pf7_1 j4 v ddext a8 gnd h24 iad13_a e2 is_7 ac16 pf7_2 d12 v ddext a9 gnd h25 iad13_b ad26 is_8 y26 pf7_3 a18 v ddext a13 gnd h26 iad14_a d1 iwr_a d8 pf7_4 ae3 v ddext a15 gnd n1 iad14_b ac24 iwr_b y23 pf7_5 n25 v ddext a17 gnd n2 iad15_a e4 pf0 a6 pf7_6 v2 v ddext ac14 gnd n3 iad15_b ac25 pf1 b6 pf7_7 af9 v ddext ac15 gnd n4 iad2_a c2 pf2 c6 pf7_8 af18 v ddext ac19 gnd r23 iad2_b v24 pf4_1 m1 reset_1 j1 v ddext ad14 gnd r24 iad3_a d3 pf4_2 c10 reset_2 d13 v ddext ad19 gnd t3 iad3_b w24 pf4_3 d18 reset_3 c22 v ddext ae14 gnd t24 iad4_a c1 pf4_4 ac2 reset_4 af6 v ddext ae19 gnd u1 iad4_b w25 pf4_5 l25 reset_5 t23 v ddext af14 gnd u2 iad5_a d2 pf4_6 t1 reset_6 aa1 v ddext af19 gnd u23 iad5_b w26 pf4_7 af7 reset_7 ac11 v ddext b7 gnd u24 iad6_a v4 pf4_8 ad18 reset_8 ac22 v ddext b8 gnd u25 iad6_b m26 pf5_1 m2 rfs0a j3 v ddext b9 gnd u26 iad7_a y4 pf5_2 d10 rfs0b ad20 v ddext b14 gnd w1 iad7_b n26 pf5_3 c18 rfs1 ae6 v ddext b15 gnd w2 iad8_a ad6 pf5_4 ac3 sclk0a p1 v ddext b17 gnd w3 gnd w4
rev. 0 adsp-21mod980 C30C signal ball signal ball signal ball signal ball signal ball name number name number name number name number name number v ddext b22 v ddext d17 v ddext k26 v ddint ab3 v ddint af25 v ddext c7 v ddext d22 v ddext l1 v ddint ab4 v ddint b3 v ddext c9 v ddext k1 v ddext l2 v ddint ab23 v ddint p23 v ddext c14 v ddext k2 v ddext l3 v ddint ab24 v ddint p24 v ddext c15 v ddext k3 v ddext l4 v ddint ab25 v ddint p25 v ddext c17 v ddext k4 v ddint a3 v ddint ab26 v ddint p26 v ddext d7 v ddext k23 v ddint a4 v ddint ae13 v ddint r1 v ddext d9 v ddext k24 v ddint ab1 v ddint af13 v ddint r2 v ddext d15 v ddext k25 v ddint ab2 v ddint af24 v ddint r3 ordering guide ambient temperature package package part number range processor clock description option adsp-21mod980-000 0 c to 70 c 37.5 mhz plastic ball grid array (pbga) b-352 related documents adsp-21mod980-210 multiport internet gateway processor solution. adsp-21mod family dynamic internet voice access tm (diva) voice over network solution. diva is a trademark of analog devices, inc.
rev. 0 adsp-21mod980 C31C 352-ball grid array (pbga) (b-352) detail a 0.103 (2.62) 0.093 (2.37) 0.083 (2.12) bottom view a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 25 23 21 19 17 15 13 11 9 7 5 3 1 26 24 22 20 18 16 14 12 10 8 6 4 2 (0.05) 1.27 bsc 1.25 (31.75) bsc (0.05) 1.27 bsc 1.378 (35.00) sq top view ball a1 indicator 1.209 (30.70) 1.181 (30.00) sq 1.161 (29.50) 0.048 (1.22) 0.046 (1.17) 0.044 (1.12) seating plane 0.008 (0.20) max detail a 0.035 (0.90) 0.030 (0.75) 0.024 (0.60) ball diameter 0.028 (0.70) 0.024 (0.60) 0.020 (0.50) 0.028 (0.70) 0.024 (0.60) 0.020 (0.50) notes 1. the actual position of the ball grid is within 0.012 (0.30) of the ideal position relative to the package edges. 2. the actual position of each ball is within 0.006 (0.15) of its ideal position relative to the ball grid. 3. center figures are typical unless otherwise noted. 4. controlling dimensions are in millimeters outline dimensions dimensions shown in inches and (mm). c01761C2.5C9/00 (rev. 0) printed in u.s.a.

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